October 8, 2004
2:30 - 3:30, LH 102

A Small Fast Local Instruction Scheduler for Itanium

Arch Robison

Abstract:
The Itanium-2 processor issues a group of up to 6 instructions per cycle. Because Itanium-2 is an in-order machine with explicit instruction-level parallelism, compilers have the power (and duty) to specify the instruction groups. However, various constraints limit what groups can be issued in parallel. These constraints include available functional units, Itanium's VLIW instruction encoding, and quirky interactions between the two.

This talk surveys the complexities of instruction scheduling on Itanium-2, and how to conquer this complexity by adapting published state-machine techniques. The hard work can be done off-line by concise but slow code that produces state machine tables. These tables guide a remarkably small and fast local scheduler that is ideal for environments requiring quick generation of reasonably good code.