'{$STAMP BS2}
'------------------------------------------------------------------------
'D STAMP PROGRAM 7C - RECEIVES CONTROL & SENDS STATE

'------------------------------------------------------------------------
'CURRENT MICROINSTRUCTION & ITS MEANING
'
'uinst		OUT	LATCH	 MEM_ALU	CY_UPC		UPC_OFFSET
'		0 =None	0  =None 		0=None
'address	1 =ACC	1  =ACC	 0=Hi-Z		1=CYF Out	must add
'is 16-bit	2 =ONE	2  =A	 1=Read		2=CYZ Out	this 8-bit
'		4 =ZERO	4  =B	 2=Sel		4=CYF Lat	value to
'		8 =PC	8  =PC	 3=Write	   0=UPC	"base" to
'		16=MAR	16 =MAR	     0=Nop	   1=IR		get address
'		32=MDR	32 =MDR	     1=Add			of byte in
'		64=TEMP	64 =TEMP     2=And			EEROM
'			128=IR	     4=Or
'				     8=Not
'

reg_out		var byte
reg_latch	var byte

mem_alu		var byte
mem_ops		var mem_alu.nib1
alu_ops		var mem_alu.nib0

cy_upc		var byte
carry_ops	var cy_upc.nib1
upc_sel		var cy_upc.bit0

next_upc	var byte


'------------------------------------------------------------------------
'DECLARATIONS TO READ MICROCODE FIELDS

none		con 0
acc		con 1
one		con 2
zero		con 4
pc		con 8
mar		con 16
mdr		con 32
temp		con 64
ir		con 128
a		con 2
b		con 4
hiz		con 0
mread		con 1	'different from KSTAMP
msel		con 2	'because the upper nib
mwrite		con 3	'is extracted
nop		con 0
gadd		con 1
gand		con 2
gor		con 4
gnot		con 8
cyf		con 1	'different from KSTAMP
cyz		con 2	'because the upper nib
lcyf		con 4	'is extracted
sel_upc		con 0
sel_ir		con 1


'------------------------------------------------------------------------
'GEMINI REGISTERS

alu_out		var word
alu_byte	var alu_out.byte0
cyf_		var alu_out.bit8
cyz_		con 0
acc_		var byte
a_		var byte
b_		var byte

zero_		con 0
one_		con 1
pc_		var byte
mar_		var byte
mdr_		var byte
temp_		var byte
ir_		var byte

'------------------------------------------------------------------------
'SIMULATOR INDEX REGISTER FOR LOOKDOWN, LOOKUP, AND BRANCH

index		var byte
nomatch		con 255		'trap value if no match during LOOKDOWN

'------------------------------------------------------------------------
'SIMULATOR VARIABLES TO CONTROL DISPLAY & THROTTLE DISPLAY SPEED

button_wkspace	var byte
timer_var	var word

'------------------------------------------------------------------------
'SIMULATOR FLAG TO CONTROL DOUBLE LATCHING OF A/B & ACC
'IN SAME CYCLE, AND CONTROL SOME DISPLAYED VALUES

accflag		var bit
no_out_flag	var bit
display_mem	var bit

'------------------------------------------------------------------------
'SIMULATOR TEMPORARY STORAGE FOR CARRY FLAG

carry_temp	var bit

'------------------------------------------------------------------------
'GEMINI REGISTER & MEMORY BUS

bus		var byte

null		con 255		'undriven bus value

'------------------------------------------------------------------------
'GEMINI MEMORY

'------------------------------------------------------------------------
'LINE FEED FOR SERIAL PORT
lf con 10
'------------------------------------------------------------------------

begin	data lda,	con_zero
	data sta,	tempcnt

loop	data lda,	tempcnt
	data adda,	con_one
	data sta,	tempcnt
	data anda,	low_nib
	data ora,	high_nib
	data nota
	data sta,	logic_value
	data brc,	begin

	data lda,	branch_always
	data adda,	con_one
	data brc,	loop

counter	data 256-3
tempcnt	data (1)
logic_value data (1)
branch_always data 255
con_one       data 1
con_zero      data 0
con_three     data 3
high_nib      data $F0
low_nib       data $0F

ram	data (256-ram)

mem_addr	var byte
mem_value	var byte

'------------------------------------------------------------------------
'MACHINE CODE DECLARATIONS

noop	con %00000000
lda	con %10000000
sta	con %01000000
adda	con %11000000
adca	con %00100000
anda	con %10100000
ora	con %11100000
nota	con %00010000
brc	con %00110000

'------------------------------------------------------------------------
'GEMINI DATAPATH SIMULATOR

recv_uinst:

high 7 'charges capacitor for RCTIME instruction

serin 15, 32, 1000, send_state, [wait("d"), reg_out, reg_latch, mem_alu, cy_upc, next_upc]

button 6,1,255,0,button_wkspace,0,toggle_done
'change microcode display flag
toggle 0

toggle_done:

high 8 'turns on LED

'------------------------------------------------------------------------
'DISPLAY CURRENT MICROINSTRUCTION

display_microinst:

rctime 7,1,timer_var
lookdown timer_var, >[6500,4500,2000,1000,750,400,200,50,0], index
lookup index, [2000,750,500,300,200,100,60,30,0], timer_var
pause timer_var

if out0=0 then register_output

debug hex2 reg_out, " "
debug hex2 reg_latch, " "
debug hex2 mem_alu, " "
debug hex2 cy_upc, " "
debug hex2 next_upc, ": "


'------------------------------------------------------------------------
'SIMULATE & DISPLAY DATA TRANSFERS & ALU FUNCTIONS

register_output:

no_out_flag=0
index=nomatch
lookdown reg_out, =[none,acc,zero,one,pc,mar,mdr,temp], index

if out0=1 then display_reg_out
'else don't display
branch   index, [no_out,acc_out,zero_out,one_out,pc_out,mar_out,mdr_out,temp_out]
goto memory_read

display_reg_out:
branch   index, [no_out,dacc_out,dzero_out,done_out,dpc_out,dmar_out,dmdr_out,dtemp_out]
goto memory_read 'if index=nomatch


no_out:		no_out_flag=1
		goto memory_read

dacc_out:	debug "ACC>>"
acc_out:	bus=acc_
		goto register_latching

dzero_out:	debug "ZERO>>"
zero_out:	bus=zero_
		goto register_latching

done_out:	debug "ONE>>"
one_out:	bus=one_
		goto register_latching

dpc_out:	debug "PC>>"
pc_out:		bus=pc_
		goto register_latching

dmar_out:	debug "MAR>>"
mar_out:	bus=mar_
		goto register_latching

dmdr_out:	debug "MDR>>"
mdr_out:	bus=mdr_
		goto register_latching

dtemp_out:	debug "TEMP>>"
temp_out:	bus=temp_
		goto register_latching


memory_read:

if mem_ops<>mread then register_latching

'else read value from memory location

if out0=0 then dont_display_mem
		debug "MEMR>>"
dont_display_mem:
		read mem_addr, bus
		no_out_flag=0

register_latching:

accflag=0
index=nomatch

lookdown reg_latch, =[none,acc,a,b,acc+a,acc+b,pc,mar,mdr,temp,ir], index

if out0=1 then display_latch_reg
'else don't display
branch   index, [nol,accl,al,bl,accal,accbl,pcl,marl,mdrl,templ,irl]
goto memory_write 'if index=nomatch

display_latch_reg:
branch   index, [nol,accl,dal,dbl,daccal,daccbl,dpcl,dmarl,dmdrl,dtempl,dirll]
goto memory_write 'if index=nomatch





nol:		'debug "??? "
		'debug hex2 bus
		goto memory_write

accl:		accflag=1
		goto alu_operations

daccal:		accflag=1
dal:		debug "A "
		debug hex2 bus
		goto al
accal:		accflag=1
al:		a_=bus
		goto alu_operations

daccbl:		accflag=1
dbl:		debug "B "
		debug hex2 bus
		goto bl
accbl:		accflag=1
bl:		b_=bus
		goto alu_operations

dpcl:		debug "PC "
		debug hex2 bus
pcl:		pc_=bus
		goto alu_operations

dmarl:		debug "MAR "
		debug hex2 bus
marl:		mar_=bus
		goto alu_operations

dmdrl:		debug "MDR "
		debug hex2 bus
mdrl:		mdr_=bus
		goto alu_operations

dtempl:		debug "TEMP "
		debug hex2 bus
templ:		temp_=bus
		goto alu_operations

dirll:		debug "IR "
		debug hex2 bus
irl:		ir_=bus
		goto alu_operations


memory_write:

if mem_ops=mwrite then write_location
'else write address
if mem_ops<>msel then alu_operations
if out0=0 then dont_display_addr
debug "ADDR "
debug hex2 mem_addr

dont_display_addr:
mem_addr=bus
goto alu_operations

write_location:
if out0=0 then dont_display_memw
debug "MEMW  "
debug hex2 bus

dont_display_memw:
write mem_addr,bus
goto alu_operations


alu_operations:

index=nomatch
lookdown alu_ops, =[nop,gadd,gand,gor,gnot], index

if out0=1 then display_alu_op
'else don't display
branch   index, [latch_alu,alu_add,alu_and,alu_or,alu_not]
goto send_state 'if index=nomatch

display_alu_op:
branch   index, [latch_alu,dalu_add,dalu_and,dalu_or,dalu_not]
goto send_state 'if index=nomatch

alu_add:	carry_temp=cyf_
		if (carry_ops and cyz)=cyz then add_no_carry
		'else add_with_carry
		alu_out=a_+b_+carry_temp
		goto latch_carry

add_no_carry:	alu_out=a_+b_
		goto latch_carry

dalu_add:	carry_temp=cyf_
		if (carry_ops and cyz)=cyz then dadd_no_carry
		'else add_with_carry
		alu_out=a_+b_+carry_temp
		debug cr,lf,tab,tab,"ADC"
		goto latch_carry

dadd_no_carry:	alu_out=a_+b_
		debug cr,lf,tab,tab,"ADD"


latch_carry:	if (carry_ops and lcyf)=lcyf then latch_alu
		cyf_=carry_temp
		goto latch_alu

dalu_and:	debug cr,lf,tab,tab,"AND"
alu_and:	alu_byte = a_ & b_
		goto latch_alu
		

dalu_or:	debug cr,lf,tab,tab,"OR "
alu_or:		alu_byte = a_ | b_
		goto latch_alu
		
dalu_not:	debug cr,lf,tab,tab,"NOT"
alu_not:	alu_byte = ~a_
		

latch_alu:	if accflag=0 then send_state
		acc_=alu_out
		if out0=0 then dont_send_cr
		debug ">>ACC "
		debug hex2 acc_


'------------------------------------------------------------------------
'SEND IR & CYF BACK TO K STAMP CONTROLLER

send_state:

if out0=0 then dont_send_cr
debug cr,lf

dont_send_cr:


'------------------------------------------------------------------------
'DISPLAY CURRENT MACHINE INSTRUCTION & ACC


if reg_latch<>ir then send_state2

debug hex2 pc_-1, ": "

display_mem=1
lookdown ir_,=[nop,lda,sta,adda,adca,anda,ora,nota,brc],index
branch index,[nopm,ldam,stam,addm,adcm,andm,oram,notam,brcm]
goto send_state2

nopm:	debug "NOP"
	display_mem=0
	goto display_acc

ldam:	debug "LDA"
	goto display_acc

stam:	debug "STA"
	goto display_acc

addm:	debug "ADD"
	goto display_acc

adcm:	debug "ADC"
	goto display_acc

andm:	debug "AND"
	goto display_acc

oram:	debug "OR "
	goto display_acc

notam:	debug "NOT"
	display_mem=0
	goto display_acc

brcm:	debug "BRC"
	goto display_acc

display_acc:

debug tab, "ACC=", hex2 temp_

if display_mem=0 then display_finished
if ir_<>brc then display_deref

'else fetch branch address
read pc_, mem_value
debug tab, "ADDR: ", hex2 mem_value
goto display_finished

display_deref:

read pc_, mem_value
debug tab, hex2 mem_value, ":   "
read mem_value,mem_value
debug hex2 mem_value

display_finished:

debug cr,lf


send_state2:

serout 15,32+$8000,["k", ir_, cyf_, timer_var]

low 8

goto recv_uinst
end