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| Issue 1294-3 |
| US 6,895,538 B2 |
| Method for testing a device and a test configuration including a device with a test memory |
| Alexander Benedix, München (Germany); Henning Hartmann, Oberhaching (Germany); Reinhard Düregger, Poing (Germany); and Wolfgang Ruf, Friedberg (Germany) |
| Assigned to Infineon Technologies AG, Munich (Germany) |
| Filed on Jul. 18, 2001, as Appl. No. 9/907,694. |
| Claims priority of application No. 100 34 878 (DE), filed on Jul. 18, 2000. |
| Prior Publication US 2004/0015313 A1, Jan. 22, 2004 |
| Int. Cl.7G11C 29/00 |
| U.S. Cl. 714—723 [365/201] | 12 Claims |
| 1. A method for testing a semiconductor memory, which comprises:
providing the semiconductor memory with a nonvolatile memory and a multiplicity of individual memory cells;
using a test method to test the semiconductor memory and to determine test results, and for testing the individual memory
cells with regard to a correct operation mode;
storing the test results in the nonvolatile memory in the semiconductor memory to make the test results available to the semiconductor
memory throughout the service life of the semiconductor memory; and
storing an identifier in the nonvolatile memory to indicate the test method used to determine the test results.
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