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During each frame, a set of isochronous, bulk, control and interrupt transfers may be performed. Each of these transfers is encapsulated by a transfer descriptor. The way the transfer descriptors are laid out is different for isochronous transfers as compared to other types for transfers. For isochronous tranfers, the TDs are laid out sequentially in a list as follows:
IsoTD1 -> IsoTD2 -> .....-> IsoTDn
But for other types of transfers, these are pointed to by seperate elements called queue heads. Putting all these together, the transfer schedule looks as follows:
Figure 4:
Transfer Schedule
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The order of execution of various types of transfers is implicit in the layout. It is evident that the initial set of transfers to take place is those relating to the isochronous type. After completing all the isochronous ones, there are two ways in which the rest of the TDs in the queue heads may be executed. First is depth-wise, in which case all the interrupt TDs are executed after which the control and finally the bulk. The other option is breadth-wise, in which case the first TD in each of the interrupt ,control , and bulk is executed after which the second TD in each is taken up and so on.
By changing the relative numbers of the TD's of various types in each frame, the system software can alter the bandwidth allocated to each of the different tranfer types. The specification states that isochronous needs to be allocated at least 80% and control at least 5% of the bandwidth. The software also needs to ensure that it does not try to schedule more TD's in one frame than is possible to transfer. It needs to take into account the actual speed of the transfer to estimake the time required for the transfers.
In course of normal execution, the host controller executes frame sequentially in periods of 1 millisecond. However the COMMAND register has a DEBUG bit, which on being set makes the host controller stop after execution of each frame, which allows examining the values of the different registers at the end of each frame.
Next: Control Transfers
Up: Host Controller
Previous: Transfer Schedule
Bhanu Nagendra P.
2003-07-28