 |
 |
|
|
|
|
|
|
Home |
|
Geoffrey Brown
Professor and Director of Undergraduate Studies
Office address: Lindley Hall 330B, Indiana University, Bloomington IN, 47405 USA Office phone: 812-855-4207 Department fax: 812-855-4829 SIP Phone TeachingB441 Digital Design. Spring 2008 B649 Ensuring Longterm Access to Digital Information. Spring 2007 [C - H]335 Computer Structures Fall 2006, Fall 2007. p436 Introduction to Operating Systems Fall 2006 b649 Concurrent Programming Languages for System Design Spring 2004 A major undertaking for the past two years has been the development of a radically redesigned computer structures class (c335) which has as its laboratory component a small robot built from a children's toy Goofy Giggles. The focus of this course is to build a bridge from a (relatively) high-level language (C) to assembly code and its execution by a processor. Course Spec We are currently revising this course to use the ARM7 processor which is widely used in embedded systems such as cell phones.Research InterestsDigital system design methodology including formal verification, software/hardware co-design, and reconfigurable computing. Digital preservation. My current research involves three primary areas. The first is the development of system software to simplify the configuration, debugging, and management of deeply embedded processors in system on chip (SoC) environments and also in networks of sensors. The second area is the use of model checking tools to specify and verify cross-clock domain protocols such as synchronizers and data communication circuits. The third area is the use of emulation to enable preservation of digital documents. The approach we are taking for embedded system software builds upon the distributed file system model of the Plan 9 and Inferno Operating Systems by treating all system resources as virtual "files". The fundamental advantage of this approach is that it provides a familiar object model while requiring only a very lightweight protocol. Our work on cross-clock domain protocols has demonstrated that it is possible to quickly verify real-time protocols using an off-the-shelf model checker (SAL) that uses satisfiability-modulo-theories (SMT). Previous efforts utilizing conventional theorem provers required significant human (months vs days) and computer resources (hours vs seconds) than our approach. I am also exploring the use of off-the-shelf emulation and virtual machine environments to support the digital archiving of documents that require their original (obsolete) software for access. For example the US Government Printing Office began distributing vital statistics on CDROM with embedded proprietary software about 15 years ago - accessing these data requires running the embedded software. To see the current state of our online collection of GPO CDRoms - http://cgi.cs.indiana.edu/~geobrown/svp We've recently performed a study of 200,000 Office documents to determine their resource requirements (fonts, helper applications, etc.) and are undertaking a study with the Koninklijke Bibliotheek (Netherlands National Library) to apply our analysis tools to articles from their archive. The KB is the digital repository for several major scientific publishers. Prior to my return to academia in 2003, I spent seven years in industry where I was one of the lead architects of the Lx embedded VLIW microprocessor developed in an HP Laboratories/ST Microelectronics partnership and is the architecture for the in the ST210, ST220, ST230, and ST231 processors. These processors are embedded in many of ST's consumer electronics chips often with multiple processor instances. For example, there are three of these processors in each STM8000 stm8000.pdf DVD recorder chip. The Lx architecture is also used in digital video recorder chips (stx5524, stx5525, stm8010), set top box decoders (sti5300, sti5301), and in a new series of HD H264 set top box chips (stb7100, stb7109, stb7200). I also worked as a software architect for several networking startups, most recently as chief architect of Sockeye Networks. At Sockeye Networks I developed a system for Internet address clustering to support intelligent route optimization. This system allowed Sockeye Networks to save millions of dollars by replacing data purchased by other companies. My current work is a continuation of my long history of studying design, verification, and synthesis techniques for digital systems. I performed early and widely cited work on the design of self-stabilizing systems which have the desirable property that, when started in any state, are guaranteed to converge to a desirable state in finite time. My work on the design and verification of multiprocessor cache algorithms, in particular "Lazy Caching" was the subject of a special issue of Distributed Computing. I've also developed techniques to verify hardware synthesis algorithms.Selected PublicationsDigital Preservation
Verification of Cross Clock Domain Protocols
Embedded System Software
VLIW Microprocessor
Internet Address Clustering
Self-Stabilization
Cache Consistency
Hardware Synthesis
File translated from TEX by TTH, version 3.61. On 10 Apr 2008, 09:19. |
|
|
|
|
|
|
|
|
|
Page Owner: Geoffrey Brown
Last Modified: Apr 10, 2008 9:19am |
IU Computer Science Department
Email: info@IU CS Department |
|
|
|
