Library IEEE, DZX;
Use IEEE.std_logic_1164.all;
Use DZX.Logic_Utils.all;
Use DZX.Bit_Arith.all;
Use DZX.Attributes.all;

entity ITLC is
  port (IX	: in X01Z := '0';  -- island exit sensor
	IE	: in X01Z := '0';  -- island entrance sensor
	MX	: in X01Z := '0';  -- mainland exit sensor
	ME	: in X01Z := '0';  -- mainland entrance sensor
	CLK	: in X01Z := '0';  -- system clock
	RESET	: in X01Z;	   -- system wide reset
	MRL	: out X01Z := '0'; -- mainland red light
	MGL	: out X01Z := '0'; -- mainland green light
	IRL	: out X01Z := '0'; -- island red light
	IGL	: out X01Z := '0'  -- island green light
       );
end ITLC;

architecture itlc_arch of ITLC is
  signal IU, MU, IY, MY, IR, MR, IG, MG, TCInc, TCDec, ICInc, ICDec : X01Z := '0';
  signal TCEnb, TCDU, ICEng, ICDU : X01Z := '0';
  signal IC_val, TC_val : integer range 0 to 16;

  component Side_CNTL
    port(CLK, RESET. SE, SX, SG, SY : in X01Z;
    	 Res_Level : in integer range 0 to 16;
	 SRL, SGL, SU, SR, STCD, STCI, SIC : out X01Z );
  end component;

  component Tunnel_CNTL
    port(CLK, RESET, IR, MR, IU, MU : in X01Z;
	 IC_val, TC_val : in integer range 0 to 16;
	 IY, MY, IG, MG : out X01Z );
  end component;

  component UD_CNT
    port(CLK, RESET, Enable, UD : in X01Z;
	 Q : out integer range 0 to 16;
  end component;

begin

ICNTL : Side_CNTL port map (CLK,RESET,IE,IX,IG,IY,0,IRL,IGL,IU,IR,ITCD,ITCI,IIC); 
MCNTL : Side_CNTL port map (CLK,RESET,ME,MX,MG,MY,IC_val,MRL,MGL,MU,MR,MTCD,MTCI,MIC); 
TCNTL : Tunnel_CNTL port map (CLK,RESET,IR,MR,IU,MU,IC_val,TC_val,IY,MY,IG,MG);
TC    : UD_CNT port map (CLK,RESET,TCEnb,TCDU,TC_val);
IC    : UD_CNT port map (CLK,RESET,ICEnb,ICDU,IC_val);

process(ITCI, ITCD, MTCI, MTCD) 

begin
  TCDU <= ITCD or MTCD;
  TCEnb <= not ((ITCI or MTCI) xor (ITCD or MTCD));  
end process;

process(IIC, MIC)
  ICDU <= IIC;
  ICEnb <= not (MIC or IIC);
end process;

end itlc_arch;Library IEEE, DZX;
Use IEEE.std_logic_1164.all;
Use DZX.Logic_Utils.all;
Use DZX.Bit_Arith.all;
Use DZX.Attributes.all;

entity Side_CNTL is 
  port (CLK	  : in X01Z := '0'; -- system clock
  	RESET	  : in X01Z;	    -- system wide reset
	SE 	  : in X01Z := '0'; -- entrance sensor
	SX  	  : in X01Z := '0'; -- exit sensor
	SG 	  : in X01Z := '0'; -- grant signal
	SY 	  : in X01Z := '0'; -- yield signal
	Res_Level : in integer range 0 to 16; -- value of max resource usage
	SRL   	  : out X01Z := '0'; -- red light signal
	SGL   	  : out X01Z := '0'; -- green light signal
	SU   	  : out X01Z := '0'; -- in use signal
	SR   	  : out X01Z := '0'; -- request signal
	STCD   	  : out X01Z := '0'; -- tunnel counter decrement
	STCI   	  : out X01Z := '0'; -- tunnel counter increment
	SIC 	  : out X01Z := '0'; -- island counter change
       );
end Side_CNTL;

architecture side_arch of Side_CNTL is
  type STATE_TYPE is (RED, EXITING, GREEN, ENTERING);
  signal state, new_state : STATE_TYPE;      

  process(SX, SY, SE, Res_Level, SG)
  begin
  case state is
      when RED =>
	SRL <= '1';
 	SGL <= '0';
	SU <= '0';
	STCI <= '0';
	SIC <= '0';
	if SX = '1' then
	   new_state <= EXITING;
	   STCD <= '1';
        else
	   STCD <= '0';
	   if SG = '1' then
	      new_state <= GREEN;
	   else
	      new_state <= RED;
    	   end if;
   	end if;

      when EXITING =>
	SRL <= '1';
 	SGL <= '0';
	SU <= '0';
	STDC <= '0';
	STCI <= '0';
	SIC <= '0';
	if SX = '1' then
	   new_state <= EXITING ;
	else
	   new_state <= RED;
	end if;

      when GREEN =>
	SRL <= '0';
 	SGL <= '1';
	SU <= '1';
	STCD <= '0';
	if Res_Level /= "1111" then
	   if SY = '0' then
	      if SE = '1' then 
		 new_state <= ENTERING;
		 STCI <= '1';
		 SIC <= '1';
	      else
		 new_state <= GREEN;
		 STCI <= '0';
		 SIC <= '0';
	      end if;
	   else	
	      new_state <= RED;
	      STCI <= '0';
	      SIC <= '0';
	   end if;
        else
	   new_state <= RED;
	   STCI <= '0';
	   SIC <= '0';
   	end if;

      when ENTERING =>
	SRL <= '0';
 	SGL <= '1';
	SU <= '1';
	STCD <= '0';
	STCI <= '0';
	SIC <= '0';
      	if SE = '1' then
	   new_state <= ENTERING;
	else
	   new_state <= GREEN;
	end if;

      end case;
  end process;

  process(RESET, CLK, new_state)
  begin
      if RESET = '1' then
	state <= RED ;
      else
	if CLK'event and CLK = '1' then
	    state <= new_state;
	end if;
      end if;
  end process;

end side_arch;Library IEEE, DZX;
Use IEEE.std_logic_1164.all;
Use DZX.Logic_Utils.all;
Use DZX.Bit_Arith.all;
Use DZX.Attributes.all;

entity Tunnel_CNTL is 
  port (CLK	  : in X01Z := '0'; -- system clock
  	RESET	  : in X01Z;	    -- system wide reset
	IR 	  : in X01Z := '0'; -- island requested tunnel
	MR  	  : in X01Z := '0'; -- mainland requested tunnel
	IU 	  : in X01Z := '0'; -- island using tunnel
	MU 	  : in X01Z := '0'; -- mainland using tunnel
	IC_val	  : in integer range 0 to 16; -- value of island counter
	TC_val	  : in integer range 0 to 16; -- value of tunnel counter
	IY   	  : out X01Z := '0'; -- island yield
	MY   	  : out X01Z := '0'; -- mainland yield
	IG   	  : out X01Z := '0'; -- island granted tunnel
	MG   	  : out X01Z := '0'  -- mainland granted tunnel
       );
end Tunnel_CNTL;

architecture tunn_arch of Tunnel_CNTL is
  type STATE_TYPE is (DISPATCH, IUSE, MUSE, ICLEAR, MCLEAR);
  signal state, new_state : STATE_TYPE;      

  process()
  begin
  case state is
      when DISPATCH =>
	IY <= '0';
	MY <= '0';
	if IR = '0' then
	   IG <= '0';
	   if MR = '1' and IC_val < 16 then
	      if IU = '1' then
		 new-state <= IUSE;
		 MG <= '0';
	      else
		 if TC_val = 0 then
		    new_state <= DISPATCH;
		    MG <= '1';
		 else
		    new_state <= ICLEAR;
		    MG <= '0';
		 end if;
	      end if;
	   else
	      new_state <= DISPATCH;
	      IG <= '0';
	      MG <= '0';
	   end if;
	else
	   MG <= '0';
	   if MU = '1' then
	      new_state <= MUSE;
		 IG <= '0';
	   else
	      if TC_val = 0 then
		 new_state <= DISPATCH;
		 IG <= '1';
	      else
		 new_state <= MCLEAR;
		 IG <= '0';
	      end if;
	   end if;
	end if;

      when IUSE =>
	IY <= '1';
	MY <= '0';
	IG <= '0';
	MG <= '0';
	if IU = '1' then
	   new_state <= IUSE;
	else
	   new_state <= ICLEAR;
	end if;

      when MUSE =>
	IY <= '0';
	MY <= '1';
	IG <= '0';
	MG <= '0';
	if MU = '1' then
	   new_state <= MUSE;
	else
	   new_state <= MCLEAR;
	end if;

      when ICLEAR =>
	IY <= '0';
	MY <= '0';
	IG <= '0';
	if TC_val = 0 then
	   new_state <= DISPATCH;
	   MG <= '1';
	else
	   new_state <= ICLEAR;
	   MG <= '0';
	end if;

      when MCLEAR =>
	IY <= '0';
	MY <= '0';
	MG <= '0';
	if TC_val = 0 then
	   new_state <= DISPATCH;
	   IG <= '1';
	else
	   new_state <= MCLEAR;
	   IG <= '0';
	end if;

      end case;
  end process;

  process(RESET, CLK, new_state)
  begin
      if RESET = '1' then
	state <= DISPATCH ;
      else
	if rising_edge(CLK) then
	    state <= new_state;
	end if;
      end if;
  end process;

end tunn_arch;Library IEEE, DZX;
Use IEEE.std_logic_1164.all;
Use DZX.Logic_Utils.all;
Use DZX.Bit_Arith.all;
Use DZX.Attributes.all;

entity UD_CNT is
  port (CLK	: in X01Z := '0';  -- system clock
 	RESET	: in X01Z;	   -- system reset
	Enable	: in X01Z;	   -- counter enable
	UD	: in X01Z := '0';  -- count up (if 0) or count down (if 1)
	Q	: out integer range 0 to 16
       );
end UD_CNT;
  
architecture cnt_arch of UD_CNT is
  constant MAXVAL : integer := 16;
  constant MINVAL : integer := 0;
begin
  process (CLK, Enable, UD)
    variable CNTR_VALUE : integer range 0 to 16;
    begin 
    	if RESET = '1' then
	   CNTR_VALUE := 0;
	elsif rising_edge(CLK) then
	   if Enable = '0' then
	      if UD = '0' 
		 if CNTR_VALUE < UPPERBOUND then
		    CNTR_VALUE := CNTR_VALUE + 1;
		 else 
		    CNTR_VALUE := CNTR_VALUE;
	  	 end if;
	      else
		 if CNTR_VALUE > LOWERBOUND then
		    CNTR_VALUE := CNTR_VALUE - 1;
		 else 
		    CNTR_VALUE := CNTR_VALUE;
	  	 end if;
	      end if;
	   else
	      CNTR_VALUE := CNTR_VALUE;
	   end if;
	end if;
	Q <= CNTR_VALUE;
    end process;
end cnt_arch